1. Field of the Invention
The present invention generally relates to an interface circuit, and particularly to a low jitter input buffer.
2. Description of Related Art
Major design efforts have been directed at circuit design techniques involving input circuits for memory devices. A number of solutions have been proposed.
U.S. Pat. No. 5,978,310 (Bae et al) describes an input buffer for a DRAM memory device, which removes noise from the row address strobe. The device has a data output enable, which can be delayed for a predetermined time, and which also produces a control signal for the output. There is also a buffer output for producing the noise free input according to the control signal.
U.S. Pat. No. 6,002,618 (Komarek et al) discloses an NMOS input receiver circuit for a read only memory. It includes a feedback loop to control hysteresis. There is a second stage and an additional output for the receiver. Switching noise from inside the memory is isolated and cannot be fed back into the receiver circuit to affect the TTL voltage levels. Wide, long FET sizes are used to minimize manufacture variations in the receiver switching levels.
What is still needed is a mechanism by which an input buffer works in the presence of ground noise, specifically how capacitance can be used to reduce such noise for a memory input circuit.